// round_mult.sv
// Rounds a normalized mantissa using GRS bits (round to nearest, ties to even)

module round_mult (
    input  logic [22:0] mantissa_in,   // Input mantissa (no implicit bit)
    input  logic [7:0]  exponent_in,   // Input exponent
    input  logic        guard_bit,
    input  logic        round_bit,
    input  logic        sticky_bit,
    output logic [22:0] mantissa_out,  // Rounded mantissa
    output logic [7:0]  exponent_out   // Adjusted exponent (if mantissa overflows)
);

    logic round_up;
    logic [23:0] mantissa_extended;
    logic [23:0] mantissa_rounded;

    always_comb begin
        // Concatenate implicit '1' at MSB
        mantissa_extended = {1'b0, mantissa_in};

        // Round to nearest, ties to even
        round_up = 0;
        if (guard_bit && (round_bit || sticky_bit || mantissa_in[0])) begin
            round_up = 1;
        end

        mantissa_rounded = mantissa_extended + round_up;

        if (mantissa_rounded[23]) begin
            // Overflow in rounding ? shift right and increment exponent
            mantissa_out = mantissa_rounded[23:1];
            exponent_out = exponent_in + 1;
        end else begin
            mantissa_out = mantissa_rounded[22:0];
            exponent_out = exponent_in;
        end
    end

endmodule
