264 lines
14 KiB
C
264 lines
14 KiB
C
/**************************************************************************//**
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* @file ARMCM0.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM0 Device Series
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* @version V1.07
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* @date 30. January 2012
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*
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* @note
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* Copyright (C) 2012 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef ARMCM0_H
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#define ARMCM0_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
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WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
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RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
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TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
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TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
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MCIA_IRQn = 4, /*!< MCIa Interrupt */
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MCIB_IRQn = 5, /*!< MCIb Interrupt */
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UART0_IRQn = 6, /*!< UART0 Interrupt */
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UART1_IRQn = 7, /*!< UART1 Interrupt */
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UART2_IRQn = 8, /*!< UART2 Interrupt */
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UART4_IRQn = 9, /*!< UART4 Interrupt */
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AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
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CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
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ENET_IRQn = 12, /*!< Ethernet Interrupt */
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USBDC_IRQn = 13, /*!< USB Device Interrupt */
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USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
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CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
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FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
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CAN_IRQn = 17, /*!< CAN Interrupt */
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LIN_IRQn = 18, /*!< LIN Interrupt */
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I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
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CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
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UART3_IRQn = 30, /*!< UART3 Interrupt */
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SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
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#define __CM0_REV 0x0000 /*!< Core revision r0p0 */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#include <core_cm0.h> /* Processor and core peripherals */
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#include "system_ARMCM0.h" /* System Header */
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/* ------------------- Start of section using anonymous unions ------------------ */
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#if defined(__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined(__ICCARM__)
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#pragma language=extended
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ CPU FPGA System (CPU_SYS) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
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__IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
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__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
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__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
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__I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
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__IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
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uint32_t RESERVED0[2];
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__IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
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__IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
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__IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
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uint32_t RESERVED1[3];
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__IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
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__IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
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} ARM_CPU_SYS_TypeDef;
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/* ================================================================================ */
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/* ================ DUT FPGA System (DUT_SYS) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
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__IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
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__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
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__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
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__IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
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__I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
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__I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
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} ARM_DUT_SYS_TypeDef;
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/* ================================================================================ */
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/* ================ Timer (TIM) ================ */
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/* ================================================================================ */
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typedef struct
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{
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__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
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__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
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__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
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__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
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__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
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__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
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__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
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uint32_t RESERVED0[1];
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__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
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__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
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__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
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__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
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__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
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__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
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__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
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} ARM_TIM_TypeDef;
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/* ================================================================================ */
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/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
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/* ================================================================================ */
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typedef struct
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{
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__IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
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union {
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__I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
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__O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
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};
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uint32_t RESERVED0[4];
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__IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
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uint32_t RESERVED1[1];
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__IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
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__IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
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__IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
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__IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
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__IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
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__IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
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__IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
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__IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
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__IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
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__O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
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__IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
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} ARM_UART_TypeDef;
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined(__CC_ARM)
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#pragma pop
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#elif defined(__ICCARM__)
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/* leave anonymous unions enabled */
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning restore
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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/* -------------------------- CPU FPGA memory map ------------------------------- */
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#define ARM_FLASH_BASE (0x00000000UL)
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#define ARM_RAM_BASE (0x20000000UL)
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#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
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#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
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#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
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#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
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/* -------------------------- DUT FPGA memory map ------------------------------- */
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#define ARM_APB_BASE (0x40000000UL)
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#define ARM_AHB_BASE (0x4FF00000UL)
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#define ARM_DMC_BASE (0x60000000UL)
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#define ARM_SMC_BASE (0xA0000000UL)
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#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
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#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
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#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
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#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
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#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
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#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
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#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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/* -------------------------- CPU FPGA Peripherals ------------------------------ */
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#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
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#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
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/* -------------------------- DUT FPGA Peripherals ------------------------------ */
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#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
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#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
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#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
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#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
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#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
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#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
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#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARMCM0_H */
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