\hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4}{}\section{utl\+:\+:i2c\+\_\+i$<$ virtual\+\_\+tag $>$ Class Template Reference}
\label{classutl_1_1i2c__i_3_01virtual__tag_01_4}\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}


A virtual base class specialization.  




{\ttfamily \#include $<$i2c.\+h$>$}

Inheritance diagram for utl\+:\+:i2c\+\_\+i$<$ virtual\+\_\+tag $>$\+:\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[height=2.000000cm]{classutl_1_1i2c__i_3_01virtual__tag_01_4}
\end{center}
\end{figure}
\subsection*{Public Types}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}} \{ \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09ae409eb2ba6eb6801f52763ae370c350e}{Sequence\+::\+B\+Y\+TE}} =0, 
\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a0fc437bc317835cad5faafc12a83fad5}{Sequence\+::\+A\+CK}}, 
\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a01af7e5aa5863a91810dd4e5d0e383ce}{Sequence\+::\+B\+Y\+T\+En\+A\+CK}}
 \}
\begin{DoxyCompactList}\small\item\em I2C transmit/receive sequence. \end{DoxyCompactList}\item 
using \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} = \mbox{\hyperlink{classutl_1_1i2c__i}{i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$
\begin{DoxyCompactList}\small\item\em Export type as identity meta-\/function. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Public Member Functions}
\begin{Indent}\textbf{ Get/\+Set functions}\par
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7b905fe7f0878a83d1c08a3fb95ac093}{clock}} () const
\item 
void \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7a267d84ea677bc2d11b25dc828f67a7}{clock}} (uint32\+\_\+t c)
\begin{DoxyCompactList}\small\item\em set clock frequency of the bus \mbox{[}Hz\mbox{]} \end{DoxyCompactList}\end{DoxyCompactItemize}
\end{Indent}
\begin{Indent}\textbf{ User functions}\par
\begin{DoxyCompactItemize}
\item 
void \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ad7e9c66a85ab55f80bb0977208517603}{start}} ()
\item 
void \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a86b0da49baf7d149ce5e316db186d65c}{stop}} ()
\item 
\mbox{\hyperlink{namespaceutl_a1427cb5a2b13313147a902173b91e3c1}{byte\+\_\+t}} \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a6dccb32f00830226f6782034177c7d8b}{rx\+\_\+data}} (bool ack, \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}} seq=Sequence\+::\+B\+Y\+T\+En\+A\+CK)
\begin{DoxyCompactList}\small\item\em Receive a byte from the i2c bus. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5e60b4bda2d7203aa8f2df35aa6dfa5d}{tx\+\_\+data}} (\mbox{\hyperlink{namespaceutl_a1427cb5a2b13313147a902173b91e3c1}{byte\+\_\+t}} byte, \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}} seq=Sequence\+::\+B\+Y\+T\+En\+A\+CK)
\begin{DoxyCompactList}\small\item\em Transmit a byte to the i2c bus. \end{DoxyCompactList}\end{DoxyCompactItemize}
\end{Indent}
\subsection*{Object lifetime}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a31335550747f46adabf153e9ad206882}{i2c\+\_\+i}} ()=default
\begin{DoxyCompactList}\small\item\em Allow constructor from derived only. \end{DoxyCompactList}\item 
\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5f530866d47aa343b4372da308f482dc}{i2c\+\_\+i}} (const \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} \&)=delete
\begin{DoxyCompactList}\small\item\em No copies. \end{DoxyCompactList}\item 
\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} \& \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a931323b813a653057e039416e0fd5b99}{operator=}} (const \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} \&)=delete
\item 
virtual \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a9190c053fb15634b5aab672f17d9544f}{$\sim$i2c\+\_\+i}} ()=default
\end{DoxyCompactItemize}


\subsection{Detailed Description}
\subsubsection*{template$<$$>$\newline
class utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}

A virtual base class specialization. 


\begin{DoxyParams}{Parameters}
{\em impl\+\_\+t} & = \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} \\
\hline
\end{DoxyParams}


Definition at line 140 of file i2c.\+h.



\subsection{Member Typedef Documentation}
\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!type@{type}}
\index{type@{type}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{type}{type}}
{\footnotesize\ttfamily using \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} =  \mbox{\hyperlink{classutl_1_1i2c__i}{i2c\+\_\+i}} $<$\mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}}$>$}



Export type as identity meta-\/function. 



Definition at line 142 of file i2c.\+h.



\subsection{Member Enumeration Documentation}
\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!Sequence@{Sequence}}
\index{Sequence@{Sequence}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{Sequence}{Sequence}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}}\hspace{0.3cm}{\ttfamily [strong]}}



I2C transmit/receive sequence. 

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{B\+Y\+TE@{B\+Y\+TE}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!B\+Y\+TE@{B\+Y\+TE}}}\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09ae409eb2ba6eb6801f52763ae370c350e}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09ae409eb2ba6eb6801f52763ae370c350e}} 
B\+Y\+TE&Only read/write byte \mbox{[}8 clocks\mbox{]}. \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{A\+CK@{A\+CK}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!A\+CK@{A\+CK}}}\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a0fc437bc317835cad5faafc12a83fad5}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a0fc437bc317835cad5faafc12a83fad5}} 
A\+CK&Only send/receive ack \mbox{[}1 clock\mbox{]}. \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{B\+Y\+T\+En\+A\+CK@{B\+Y\+T\+En\+A\+CK}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!B\+Y\+T\+En\+A\+CK@{B\+Y\+T\+En\+A\+CK}}}\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a01af7e5aa5863a91810dd4e5d0e383ce}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09a01af7e5aa5863a91810dd4e5d0e383ce}} 
B\+Y\+T\+En\+A\+CK&Read/\+Write byte and ack \mbox{[}9 clocks\mbox{]}. \\
\hline

\end{DoxyEnumFields}


Definition at line 145 of file i2c.\+h.



\subsection{Constructor \& Destructor Documentation}
\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a31335550747f46adabf153e9ad206882}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a31335550747f46adabf153e9ad206882}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!i2c\+\_\+i@{i2c\+\_\+i}}
\index{i2c\+\_\+i@{i2c\+\_\+i}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{i2c\+\_\+i()}{i2c\_i()}\hspace{0.1cm}{\footnotesize\ttfamily [1/2]}}
{\footnotesize\ttfamily \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::\mbox{\hyperlink{classutl_1_1i2c__i}{i2c\+\_\+i}} (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [protected]}, {\ttfamily [default]}}



Allow constructor from derived only. 

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5f530866d47aa343b4372da308f482dc}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5f530866d47aa343b4372da308f482dc}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!i2c\+\_\+i@{i2c\+\_\+i}}
\index{i2c\+\_\+i@{i2c\+\_\+i}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{i2c\+\_\+i()}{i2c\_i()}\hspace{0.1cm}{\footnotesize\ttfamily [2/2]}}
{\footnotesize\ttfamily \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::\mbox{\hyperlink{classutl_1_1i2c__i}{i2c\+\_\+i}} (\begin{DoxyParamCaption}\item[{const \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} \&}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [protected]}, {\ttfamily [delete]}}



No copies. 

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a9190c053fb15634b5aab672f17d9544f}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a9190c053fb15634b5aab672f17d9544f}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!````~i2c\+\_\+i@{$\sim$i2c\+\_\+i}}
\index{````~i2c\+\_\+i@{$\sim$i2c\+\_\+i}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{$\sim$i2c\+\_\+i()}{~i2c\_i()}}
{\footnotesize\ttfamily virtual \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::$\sim$\mbox{\hyperlink{classutl_1_1i2c__i}{i2c\+\_\+i}} (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [virtual]}, {\ttfamily [default]}}

Virtual default destructor 

\subsection{Member Function Documentation}
\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7b905fe7f0878a83d1c08a3fb95ac093}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7b905fe7f0878a83d1c08a3fb95ac093}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!clock@{clock}}
\index{clock@{clock}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{clock()}{clock()}\hspace{0.1cm}{\footnotesize\ttfamily [1/2]}}
{\footnotesize\ttfamily uint32\+\_\+t \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::clock (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption}) const\hspace{0.3cm}{\ttfamily [inline]}}

\begin{DoxyReturn}{Returns}
clock frequency of the bus \mbox{[}Hz\mbox{]} 
\end{DoxyReturn}


Definition at line 180 of file i2c.\+h.

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7a267d84ea677bc2d11b25dc828f67a7}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a7a267d84ea677bc2d11b25dc828f67a7}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!clock@{clock}}
\index{clock@{clock}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{clock()}{clock()}\hspace{0.1cm}{\footnotesize\ttfamily [2/2]}}
{\footnotesize\ttfamily void \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::clock (\begin{DoxyParamCaption}\item[{uint32\+\_\+t}]{c }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}}



set clock frequency of the bus \mbox{[}Hz\mbox{]} 



Definition at line 181 of file i2c.\+h.

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a931323b813a653057e039416e0fd5b99}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a931323b813a653057e039416e0fd5b99}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!operator=@{operator=}}
\index{operator=@{operator=}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{operator=()}{operator=()}}
{\footnotesize\ttfamily \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}}\& \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::operator= (\begin{DoxyParamCaption}\item[{const \mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_ac892faacc1566f4ca1438e3df765bcac}{type}} \&}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [protected]}, {\ttfamily [delete]}}

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a6dccb32f00830226f6782034177c7d8b}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a6dccb32f00830226f6782034177c7d8b}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!rx\+\_\+data@{rx\+\_\+data}}
\index{rx\+\_\+data@{rx\+\_\+data}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{rx\+\_\+data()}{rx\_data()}}
{\footnotesize\ttfamily \mbox{\hyperlink{namespaceutl_a1427cb5a2b13313147a902173b91e3c1}{byte\+\_\+t}} \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::rx\+\_\+data (\begin{DoxyParamCaption}\item[{bool}]{ack,  }\item[{\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}}}]{seq = {\ttfamily Sequence\+:\+:BYTEnACK} }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}}



Receive a byte from the i2c bus. 


\begin{DoxyParams}{Parameters}
{\em ack} & Optional ack bit. \begin{DoxyItemize}
\item 1 A\+CK the reception \item 0 Don\textquotesingle{}t A\+CK the reception. \end{DoxyItemize}
\\
\hline
{\em seq} & The operation sequence to execute \begin{DoxyItemize}
\item Sequence\+::\+B\+Y\+TE Receive only the byte, do not send ack clock \item Sequence\+::\+A\+CK Send only the ack bit \item Sequence\+::\+B\+Y\+T\+En\+A\+CK Receive the byte and send the ack bit \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
The byte received. 
\end{DoxyReturn}


Definition at line 203 of file i2c.\+h.

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_ad7e9c66a85ab55f80bb0977208517603}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_ad7e9c66a85ab55f80bb0977208517603}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!start@{start}}
\index{start@{start}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{start()}{start()}}
{\footnotesize\ttfamily void \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::start (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}}



Definition at line 189 of file i2c.\+h.

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a86b0da49baf7d149ce5e316db186d65c}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a86b0da49baf7d149ce5e316db186d65c}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!stop@{stop}}
\index{stop@{stop}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{stop()}{stop()}}
{\footnotesize\ttfamily void \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::stop (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}}



Definition at line 190 of file i2c.\+h.

\mbox{\Hypertarget{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5e60b4bda2d7203aa8f2df35aa6dfa5d}\label{classutl_1_1i2c__i_3_01virtual__tag_01_4_a5e60b4bda2d7203aa8f2df35aa6dfa5d}} 
\index{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}!tx\+\_\+data@{tx\+\_\+data}}
\index{tx\+\_\+data@{tx\+\_\+data}!utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$@{utl\+::i2c\+\_\+i$<$ virtual\+\_\+tag $>$}}
\subsubsection{\texorpdfstring{tx\+\_\+data()}{tx\_data()}}
{\footnotesize\ttfamily bool \mbox{\hyperlink{classutl_1_1i2c__i}{utl\+::i2c\+\_\+i}}$<$ \mbox{\hyperlink{structutl_1_1virtual__tag}{virtual\+\_\+tag}} $>$\+::tx\+\_\+data (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{namespaceutl_a1427cb5a2b13313147a902173b91e3c1}{byte\+\_\+t}}}]{byte,  }\item[{\mbox{\hyperlink{classutl_1_1i2c__i_3_01virtual__tag_01_4_a260541de452a9a653162b8b109b26c09}{Sequence}}}]{seq = {\ttfamily Sequence\+:\+:BYTEnACK} }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}}



Transmit a byte to the i2c bus. 


\begin{DoxyParams}{Parameters}
{\em byte} & The byte to send. \\
\hline
{\em seq} & The operation sequence to execute \begin{DoxyItemize}
\item Sequence\+::\+B\+Y\+TE Transmit only the byte, do not read ack bit \item Sequence\+::\+A\+CK Read only the ack bit \item Sequence\+::\+B\+Y\+T\+En\+A\+CK Transmit the byte and read the ack bit \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
Slave\textquotesingle{}s A\+CK bit \begin{DoxyItemize}
\item false Slave didn\textquotesingle{}t A\+CK \item true Slave did A\+CK \end{DoxyItemize}

\end{DoxyReturn}


Definition at line 218 of file i2c.\+h.



The documentation for this class was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
include/utl/com/\mbox{\hyperlink{i2c_8h}{i2c.\+h}}\end{DoxyCompactItemize}
